1. Field of the Invention
The present invention relates to a synchronous DRAM (hereinafter referred to as a SDRAM). More particularly, it relates to a SDRAM for high-speed operation which does not apply a burst address to a column address buffer under a burst mode operation of SDRAM, but which reduces a signal path of the SDRAM by directly applying the burst address to a register storing the prefetched data, thereby enhancing operation speed.
2. Description of the Prior Art
As for a read operation of a conventional SDRAM, if an address corresponding to a memory cell to be read is applied to the SDRAM, the address is input to a pre-decoder through an address buffer. At this time, an address transition detection circuit for detecting changes of the address generates one short pulse. In order to select a word line after a pre-decoding operation, the address operates a word line driver after passing through a row-decoder and then selects the word line. Similarly, if a column line corresponding to the selected memory cell is selected, the memory cell is selected. The data of the selected memory cell is input to a sense-amplifier via a bit line. The data amplified in the sense-amplifier is input to an output terminal through an output buffer.
As for a write operation of the conventional SDRAM, the process for selecting a memory cell is identical with the above read operation. During the write operation, the sense-amplifier and the output buffer have no function because a chip is at a write state, and a data input buffer enters in an operation state. Accordingly, the data being input to the input/output (I/O) pad is transmitted to a data bit line, and the data on the selected data bit line is input to a selected memory cell, thereby completing the write operation.
FIG. 1 is a block diagram of a conventional SDRAM. As shown in FIG. 1, the conventional SDRAM includes a burst length counter 18, a column address buffer/latch 19, column decoders 30 and 31, sense-amplifier & I/O gates 29 and 32, cell array blocks 23 and 24, data ouput buffers 25 and 26, a mode register 20, DQM controller 27 and DQ pin 28, etc. In operation, a counter starts operating when a burst address is input to the burst length counter 18, a pulse signal as long as the burst length is generated and input to the column address buffer/latch 19, thereby making a column path which passes through the column address buffer/latch 19, a column address predecoder and column decoders 30 and 31.
The afore-mentioned conventional SDRAM constructs a pipe line for a data bus sense-amplifier or a read data bus line, thereby enhancing operation speed. However, the burst address path becomes longer in this case, thereby causing a timing mismatch and a signal racing problem. Therefore, it is very difficult to design and verify a memory element, and such memory element needs requires a lot of time to develop itself.